The present invention relates generally to a variable gain control circuit and a receiver apparatus using this variable gain control circuit.
Referring to FIG. 1, there is shown a configuration of a direct conversion receiver for use in a DS-CDMA (Direct Sequence Code Division Multiple Access) mobile communication system for performing AGC (Automatic Gain Control) by a general analog voltage signal. In the figure, reference numeral 300 denotes an RF-IC which contains a baseband amplifier (or a variable gain amplifier) (the same holds with other accompanying drawings).
A signal received by a terminal apparatus (hereafter referred to simply as a terminal) at its external antenna is differentially amplified by a low-noise amplifier 301 to be divided into two. The direct current component is cut by a capacitor (this is called C-cut) and the resultant signal is down-converted from RF signal to baseband signal at a stretch by a quadrature mixer 302. At this moment, the RF signal is mixed with a signal with a local oscillation signal (LO) supplied from a local oscillator 304 divided by a divider 303 into in-phase component (I) and quadrature component (Q), so that baseband signals having in-phase component and quadrature component are generated. These baseband signals are each removed by a lowpass filter (LPF) 305 of the signal power of the interference wave of an adjacent channel for example, thereby providing only a desired wave signal. Next, each resultant baseband signal is amplified by a baseband amplifier 306 with its gain variably controlled by an analog voltage 309. An LPF 307 subsequent to the baseband amplifier 306 is a filter inserted to make a 50% roll-off characteristic downlink signal at the sender side be 100% roll-off characteristic as a total transfer function. After maximizing the S/N of the baseband signal through the LPF 307, the resultant baseband signal is quantized through an A/D converter 308 to be converted from analog to digital signal. The above-mentioned analog voltage signal 309 is also referred to as an AGC signal, which is controlled by a baseband signal processing block (not shown) so that the baseband signal received at the A/D converter 308 always has a optimum dynamic range.
However, it is difficult for the AGC control based on an analog voltage signal to provide precision AGC control due to wide variations between component parts of and between temperatures in the baseband amplifier 306. Especially, the problem of these variations is serious because the amplitude deflection of I and Q signals affects BER (Bit Error Rate) characteristic. In addition, BER characteristic is also affected by the digital noise on the board, thereby requiring to arrange an RC LPF (not shown) at the AGC input terminal.
To circumvent the above-mentioned problems, a configuration is receiving attention in which a PGA (Programmable Gain Amplifier) variable by 3-wire serial data setting is used instead of the AGC control based on the analog voltage signal 309. Three-wire signals are data, clock, and strobe signals. In synchronization with a clock signal, data are captured by shifting them in a serial manner and the captured data are latched in accordance with a strobe signal. Since the PGA is digitally controlled, it is hardly affected by the fluctuations in component part or temperature, thereby realizing precision setting of the gains of I and Q signals. Further, a high linearity of the baseband amplification block may be achieved by switching each linear resistor.
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-36358
As described above, the PGA method is advantageous in various points as the ACG controlling for the direct conversion receiver, but at the cost of the following problems.
FIG. 2 is a configuration diagram illustrating a direct conversion receiver apparatus for use in a DS-CDMA mobile communication system with its AGC control based on PGA.
Instead of the AGC control based on the analog voltage signal 309, 3-wire serial digital data 312 are set and decoded by a PGA control circuit 311, thereby discretely switching the gains of baseband amplifiers 306. A DC offset canceller circuit 310 detects the DC component at the final stage of the baseband amplifier to apply negative feedback in an analog manner, thereby canceling the DC offset (refer to Patent Document 1). Although not shown in the block diagram of FIG. 1, the DC offset canceller circuit 310 is also usually installed on the direct conversion receiver in which AGC control is executed by the analog voltage signal described with reference to FIG. 1. As described above, the PGA method decodes the 3-wire serial digital data 312 by the PGA control circuit 311 to discretely switching the gains of baseband amplifiers 306. Suppose here the case in which gains are switched from one to another by 1 dB upward.
The following briefly describes this case with reference to FIG. 3. It is supposed that, if the PGA data for the sequence of differential amplifiers configuring the a baseband amplification block change from “0111” to “1000”, the first stage amplifier which has been off be switched by the PGA control circuit 311 from 0 dB to 20 dB, the subsequent three amplifiers providing a gain which is 19 dB less than the current gain. As a total gain, only 1 dB is added. However, in this differential amplifier sequence, the discrete switching of gains causes a stepwise DC offset due to the variation in transistor pair. Depending on manufacturing processes, this DC offset may reach several mV or higher on the input basis. Hence, largely switching the gain at the initial stage of the amplifier sequence results in a fairly large DC offset at the final stage. This stepwise DC offset component due to the gain switching is not affected by the C-cut and therefore interferes the desired wave signal component, thereby deteriorating the S/N.
FIG. 4 shows how the above-mentioned stepwise DC offset interferes the desired wave signal. As shown in the figure, the stepwise DC offset component that is interfering is indicated by a hatched portion, in a wideband desired wave signal, generated by Fourier transform.
In the above-mentioned circuit shown in FIG. 2, the DC offset canceller circuit 310 is mounted, but, due to the circuit configuration based on analog negative feedback, a waveform as shown in FIG. 5 is obtained in the IQ output at the final stage. The large glitch component at gain switching shown in FIG. 5 saturates the A/D converter 308 shown in FIG. 2, thereby pushing up the moving average deviations necessary for AGC control which are computed from the received IQ signal. If the frequency of this glitch increases, the moving average deviations eventually converge to the AGC value which depends on the glitch value. Consequently, proper AGC control is not performed on each regular receive signal and therefore the level set lower than the optimum level in the A/D converter 308, resulting in a deteriorated reception characteristic due to quantization noise.
Generally, in analog DC offset canceller circuits, the time of DC level convergence is related with the cutoff frequency of the LPF at the time of DC feedback. If the cutoff frequency of the LPF is around 5 kHz, it takes around 100 microseconds or more for DC offset convergence. Hence, a method has recently been proposed in which the gain is set by the PGA and then the cutoff frequency of the LPF is temporarily lifted up to around 100 to 200 kHz for about 10 microseconds for example, thereby increasing the speed of DC offset convergence. Further, to take actions against the glitch component adversely affecting AGC control, a method has been proposed in which the IQ signal data in a period of 10 microseconds in the above-mentioned method are masked at the output stage, thereby preventing the waveform shown in FIG. 5 from being outputted.
On the other hand, the standardization is currently in progress on the DS-CDMA method at 3GPP (3rd Generation Partnership Project) and its specifications define a signal having SF (Spreading Factor)=4 as downlink DPCH (Dedicated Physical Channel) signal. In this case, the data length of one symbol is 1 microsecond, so that if the IQ signal is masked for a period of 10 microseconds as described above, about 10 symbols of data are lost.